CC8E C compiler for PIC18

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Enhanced PIC18 core

The following table shows the implemented features for the Enhanced PIC18 core

Supported 16k byte RAM/SFR addressing (64 banks of 256 bytes)
Supported Interrupt vector table
Supported Selectable interrupt vector table or traditional high/low interrupt
Supported Automatic interrupt context save
Supported Updated address range for the LFSR instruction
Supported Updated format for MOVLB instruction
Supported New long move instruction MOFFL
Supported New standard instructions ADDFSR and SUBFSR

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